rs232coincidencecounter Project Status (05/27/2019 - 14:26:00)
Project File: m.xise Parser Errors: No Errors
Module Name: rs232coincidencecounter Implementation State: Programming File Generated
Target Device: xc3s500e-4fg320
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 674 9,312 7%  
Number of 4 input LUTs 371 9,312 3%  
Number of occupied Slices 528 4,656 11%  
    Number of Slices containing only related logic 528 528 100%  
    Number of Slices containing unrelated logic 0 528 0%  
Total Number of 4 input LUTs 685 9,312 7%  
    Number used as logic 371      
    Number used as a route-thru 314      
Number of bonded IOBs 12 232 5%  
Number of BUFGMUXs 11 24 45%  
Average Fanout of Non-Clock Nets 2.19      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMon 27. May 14:23:24 201904 Warnings (0 new)0
Translation ReportCurrentMon 27. May 14:23:47 2019000
Map ReportCurrentMon 27. May 14:24:13 2019   
Place and Route ReportCurrentMon 27. May 14:25:19 2019003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMon 27. May 14:25:29 2019006 Infos (0 new)
Bitgen ReportCurrentMon 27. May 14:25:48 2019000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateTue 24. Jul 21:25:24 2018
WebTalk ReportCurrentMon 27. May 14:25:51 2019
WebTalk Log FileCurrentMon 27. May 14:25:59 2019

Date Generated: 05/27/2019 - 14:26:00